The present invention relates to detecting counter contents in a register-based counters used for time-critical applications.
Various applications use register-based counters or xe2x80x9ctimersxe2x80x9d, to determine timing. For control applications, there is a need to check when the counter reaches zero. An existing technique for detecting when a counter reaches zero involves performing a bit-wise logical OR operation. In a typical implementation, a counter is loaded with a non-zero value and triggered by a control signal to decrement the counter contents every clock cycle.
FIG. 1 schematically represents a cascaded arrangement of two-input OR gates 66 that can be used to detect a logical zero state for an 8-bit counter. The series of gates in FIG. 1 comprises 7 two-input OR gates divided into 3 stages (stages 1, 2 and 3, as indicated in FIG. 1). A corresponding series of OR gates for an nxe2x88x92bit register requires (nxe2x88x921) two input OR gates.
However, the OR-gate arrangement of FIG. 1 can cause timing violations when large counter sizes are used at high frequency. This is because the number of bits involved in the logical OR operations are correspondingly greater. The number of stages of OR gates required is the binary logarithm of the number of bits subject of the OR operation, assuming standard two-bit input OR gates are used. That is, log2n stages of OR gates are required, where n represents the number of bits subject of the OR operation. Once the input at stage 1 OR gates is stable, the total time taken to detect that all bits are zero is the sum of the propagation delays of each OR-gate stage, plus associated wire delays for each stage (that is, T1+T2+T3).
Typically, wire delays are a function of output loading and input transition time. Wire delays are generally becoming more significant because, while transistors are becoming smaller, integrated circuits are getting bigger. Wire delays are primarily due to resistance-capacitance effects. So, In new technologies also the overall delay (T1+T2+T3) is significant in timing critical applications.
FIG. 2 schematically represents an example of detecting a 16-bit binary register reaching zero. The register is loaded with a 16-bit count value. A xe2x80x9cdecrementxe2x80x9d operation is performed every clock cycle. Once the counter expires, a bit-wise OR operation on all 16 bits stored in the binary register helps to generate the control signal. The bit-wise OR operation requires a series of OR gates similar to the arrangement of FIG. 1. In this case, however, 15 two-input OR gates are required in 4 stages for the arrangement of FIG. 2.
As the counter depth increases, the number of bits involved in the OR operation increases. Consequently, the number of required two-input OR gate stages correspondingly increases, according to the relation noted above. This increase in the number of gates and can cause an undesirable delay in recognising the zero condition. This delay can be particularly undescribed in high-frequency time-critical systems.
In view of the above observations, a need clearly exists for alternative techniques for detecting counter content reaching zero in a timing critical applications.
An improved technique for detecting when a counter reaches a zero condition can be implemented as an alternative to existing logical OR-based techniques such as those described with reference to FIGS. 1 and 2.
The described technique is implemented independent of register/counter depth. The same approach can also be used to detect when a counter reaches an upper limit, for incremental (rather than decremental) counter operation.